Phase Locked Loops (PLLs), are used in a high proportion of current electronic devices, including mobile telephones and other communication equipment. In such devices there is an increasing move for reliability, cost and performance reasons to replace analogue components wherever possible with digital equivalent circuitry.
It is important that any phase ‘jitter’, (i.e. a spurious phase discrepancy) occurring in PLLs is identified and compensated for.
In the field of this invention it is known to perform only a frequency count of a PLL, and to perform a “pass/fail” test for only phase jitter, the output of the PLL not being calibrated internally.
However, this approach has the disadvantages that at least one analogue part is required. Furthermore, no cycle-to-cycle jitter measurement is performed, and there is no calibration mechanism that allows the determination of the jitter value.
A need therefore exists for a module, system and method for testing a PLL wherein the abovementioned disadvantages may be alleviated.